FPGA Based Efficient Implementation of Viterbi Decoder
نویسندگان
چکیده
It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error detection and correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a Spartan XC3S400A FieldProgrammable Gate Array efficient implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309. Keywords—Convolutional encoder, FPGA, Register Exchange, Spartan XC3S400A Board, Viterbi decoder.
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